circuit note cn-0205 circuits from the lab? reference circuits are engineered and tested for quick and easy system integration to help solve todays analog, mixed - signal, and rf design challenges. for more information and/or support, visit www.analog.com/cn0 205. devices connected/referenced ad9122 dual channel, 1.2 gsps , 16- bit, txdac? digital - to analog converter ADL5375 broadband quadrature modulator interfacing t he ADL5375 i/q modulator to the ad9122 dual channel, 1.2 gsps high speed dac rev. 0 circuits from the lab? circuits from analog devices have been designed and built by analog device s engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. however, you are solely responsible fo r testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause what soever connected to the use of any circuits from the lab circuits. (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. evaluation and desig n support circuit evaluation boards ad9122/ADL5375 evaluation board (ad9122 - m5375- ebz) design and integration files schematics, layout files, bill of materials circuit functi o n and benefits this circuit provides a simple and flexible interface between the ad9122 dual high speed tx dac digital - to - analog converter and the ADL5375 - 05 broadband i / q modulator . because the dac output s and ADL5375 - 05 i/ q modulator inputs share a common bias level of 0.5 v , there is no need for any active or p assive level shifting circuitry. the dc coupled interface facilitates i / q modulator local oscillator ( lo ) leakage compensation by the dac. the 1.2 g sps ad9122 dac sampling rate and t he wide bandwidth of the ADL5375 - 05 modulator i and q inputs ensure that both zero - if (zif) or complex - if (cif) architectures can be supported. in addition to filtering nyquist images, the baseband filter provide s excellent rejecti on of both differential - mode and common - mode dac spurs . circuit description the circuit and board shown in figure 1 and figure2 utilize the ad9122 txdac and the ADL5375 -05 wideband transmit modulator. signal biasing and scaling in the interface circuit is controlled by the four ground - referenced resistors (rbip, rbin, rbqp, rbqn) and the two shunt resistors ( rsli,rslq) , respectively. rbip 50? rbin 50? 67 66 ibbn ibbp ad9122 ADL5375-05 rbqn 50? rbqp 50? 59 58 21 22 9 10 rsli 100? rslq 100? iout1n iout1p iout2p iout2n qbbp qbbn 09740-001 low-pass filter low-pass filter figure 1. interface between the ad9122 and ADL5375 - 05 with 50 ? resistors to ground to establish the 500 mv dc bias for the ADL5375 - 05 baseband inputs (simplified schematic)
cn-0205 circuit note rev. 0 | page 2 of 9 top view ad9122 dac ADL5375 modul at or bot t om view fi lter 09740-002 figure 2. ad9122 -m 5375 - ebz evaluation board for circuit implementation the dac s full - scale output current (i fs ) is programmable from 10 ma to 30 ma. the nominal and default value is 20 ma. in this configuration , the dac outputs swing from 0 ma to 20 ma across each of the four ground - referenced 50 resistors (r b = rbip = rbin = rbqp = rbqn ). this establish es the 5 00 m v dc bias level and a full - scale voltage swing of 2 v p- p differential on each output pair (with no load) . this 2 v p- p voltage swing can be adjusted by the r l (r l = rsli = rslq) shunt resistors without affecting the 500 m v bias level. the resulting differential peak - to - peak swing at the i/ q modulator input is given by the equation [ ] [ ] lb lb fs signal rr rr iv + = 2 2 note that t he relatively high differential input impedance of the ADL5375 (typic ally > 60 k ) can be ignored when calculating this signal level . figure 3 shows the relationship between the peak - to - peak voltage swing and r l when 50 ? bias - setting resistors are used. t he a dl5375 - 05 and ad9122 are well matched in terms of dynamic range and gain. as a result, there is no need for any active gain between the devices. the i / q modulator drive level can be fine tuned as needed by adj usting the value of r l as described above . for most applications , a value of 100 for r l is recommended. this results in a full - scale signal level of 1 v p- p (dac output at 0 dbfs).
circuit note cn-0205 rev. 0 | page 3 of 9 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 100 1k 10k differential swing (v p-p) r l (?) 09740-003 figure 3 . peak -to- peak differential swing and the swing limiting resistor (r l ) with 50 ? bias - setting resistors baseb and filtering a filter must be inserted b etween the ad9122 and ADL5375 to remove n yquist images , spurs , and br oadband noise originat ing from the dac . the filter should be placed between the d c bias setting resistors and the ac swing - limiting resistor . with this configuration, the dc b ia s setting resistors (r b in figure 4) and the signal scaling resistors (r l in figure 4) conveniently set the sour ce and load resistances for the fi lt er design. f igure 4 shows a third - order bessel low -pass filter with a ?3 db frequency of 10 mhz. matching input and output impedances of the filter make s the filter design eas y and result s in better passband flatness , which allows wide bandwidth filter designs . in th is example, the shunt resistor chosen is 100 ?, producing an ac swing of 1 v p - p differential. the frequency response of this filter is shown in figure 5 . rbip 50? rbin 50? 67 66 21 22 ibbn ibb p ad9122 ADL5375-05 rbqn 50? rbq p 50? 59 58 9 10 rsli 100? rslq 100? out1_n out1_p out2_p out2_n qbb p qbbn lpi 771.1nh lni 771.1nh 53.62pf c1i 350.1pf c2i lnq 771.1nh lpq 771.1nh 53.62pf c1q 350.1pf c2q 09740-004 figure 4. dac modulator interface with 10 mhz third - order, bessel filter 1 10 100 ?60 ?50 ?40 ?30 ?20 ?10 0 0 6 12 18 24 30 36 group delay (ns) frequency (mhz) magnitude (db) magnitude group delay 09740-005 figure 5. frequency response for dac modulator interface with 10 mhz third - order bessel filter filtering for complex if (cif) applications figure 6 shows the frequency response of the ADL5375 baseband i and q inputs. because th is device has a wide and flat frequency response ( ?3 db point = 750 mhz), it is well suited to c omplex if (cif) applications where the output signal from the dac has been digitally upconverted. in cif applications, a low - pass nyquist filter is still desirable , primarily because the dc bias level can be pr eserved from the dac output to the m odulator input . the filter topology shown in fig ure 7 is a 5 th order butterworth filter with a 300 mhz corner frequency and is the recommended filter topology . a purely differential filter can reject differential - mode im ages, spur s , and noise from the dac . using two capacitor s with their common connection grounded ( c2 and c4 in figure 7 ) divert s some of the common - mode current to ground and result s in better common - mode rejection of high - frequency signals than would be ob tained with a purely differential filter . the simulated and measured responses of this filter are shown in figure 8 and figure 9 . the measured flatness is 0.6 db from dc to 250 mhz and 0.4 db from 125 mhz to 250 mhz . this data was taken with the ad9122 i nverse s inc function o n. in this configuration, figure 10 shows the common - mode rejection performance of the 2 f dac common - mode spur vs. common - mode frequency with and without if filter shown in figure 7.
cn-0205 circuit note rev. 0 | page 4 of 9 ?6.0 ?5.0 ?4.0 ?3.0 ?2.0 ?1.0 0 1.0 1m 10m 100m 1g baseband frequenc y response (db) bb frequenc y (hz) 09740-006 figure 6 . baseband (bb) frequency response of ADL5375 - 05 rbip 50? rbin 50? 67 66 c1i 3.6pf c2pi 22pf c4pi 3pf c2ni 22pf c4ni 3pf l1pi 33nh l2pi 33nh ibbn ibbp ad9122 ADL5375-05 rbqn 50? rbqp 50? 59 58 rsli 100? rslq 100? iout1n iout1p iout2p iout2n qbbp qbbn 09740-007 l1ni 33nh l2ni 33nh c3i 6pf c1q 3.6pf c2nq 22pf c4nq 3pf c2pq 22pf c4pq 3pf l1nq 33nh l2nq 33nh l1pq 33nh l2pq 33nh c3q 6pf 21 22 9 10 figure 7. recommended dac modulator interface topology with fc = 300 mhz fifth - order, butterworth f ilter 0 ?5 ?10 ?15 ?20 ?25 1 10 100 500 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 magnitude (db) group delay (ns) frequency (mhz) magnitude group delay 09740-008 figure 8 . frequency response for dac modulator interface with 300 mhz fifth - order b utterworth filter (simulated) ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 fi l ter response (dbm) frequenc y (mhz) 09740-009 figure 9. measured frequency response for dac modulator interface with 300 mhz fifth - order b utterworth filter ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 300 400 500 600 700 800 900 1000 output power of common mode (dbm) common mode frequenc y (mhz) 09740-010 no fi lter with fi lter figure 10. measured common - mode rejection performance at ADL5375 - 05 rf output w ith filter and w ithout filter
circuit note cn-0205 rev. 0 | page 5 of 9 09740-0 11 figure 11 . spread s heet to c alculate modulator output power calculating the o utput p ower of the ad9122 and the ADL5375 in addition to the bia s- setting and signal scaling resistors, the power level at the output of the ADL5375 is a function of the dacs digital backoff level (dbfs), the signals peak - to - average ratio , the dac s full - scale current, t he insertion loss of the nyquist filter, and i/q modulator s voltage gain. the spreadsheet shown in figure 11 can be used to make this calculation. this spreadsheet can be downloaded using the following url: www.analog.com/cn0205 - powercalculator . level shifting to drive t he a dl 5375- 15 the ADL5375 - 15 requires a dc bias level of 1 500 mv. other than the difference in bias levels, the ADL5375 -05 and ADL5375 - 15 are identical. to drive the ADL5375 - 15 from the ad9 122, either a passive or active level - shifting network mu st be used . the p assive level shifting network shown i n figure 1 2 uses four series resistors along with four pull - up resistors to achieve a bias level of 1500 mv at the ADL5375 -15 input . t his passive level shifting network introduces a loss of ap proximately 2 db in the signal level . an active level shifting circuit would use a dual - differential amplifier , such as ada4938 , where placing 1500 mv on the vocm pin sets the output dc bias level. in this approach, however, the interface bandwidth is limited by the op amp. rbip 45.3? rbin 45.3? 67 66 21 22 out1_n out1_p ibbn ibb p 5v ad9122 ADL5375-15 rlip 3480? rlin 3480? rbqn 45.3? rsqp 1k? rbqp 45.3? 59 58 9 10 out2_p out2_n qbb p qbbn 5v rlqn 3480? rlqp 3480? rsqn 1k? rsip 1k? rsin 1k? 09740-012 figure 12. passive level - shifting network for biasing ADL5375 - 15 from the ad9122 txda c as previously mentioned, i t is necessary to put a f ilter between ad9122 and ADL5375 - 15. the lc filter can be located anywhere between the dac termination resistors (r1 in figure 13) and the ac swing - limiting resistor (r4 in f igure 13 ) . however, the circuit in figure 13 allows flexibility in the design of the level shifting circuit with low loss by r2 and a high driving level to modulator. it also allows a matched filter at source and load impedance. figure 1 3 is the recommended passive level - shifting network with filter .
cn-0205 circuit note rev. 0 | page 6 of 9 ad9122 lc fi lter iout_ p r1 r1 r2 r2 a a b b iout_n ADL5375-15 required dc leve l b = 1.5v r3 r4 r3 v1 09740-013 figure 13. recommended passive level - shifting network with lc filter the differential source impedance and load impedance of the filter ar e 2 ( r1 + r2 ) and 2 { r3 ||( r4 /2 )} , respectively . the s ingle- ended i mpedance seen by dac is r1 ||{ r2 + r3 ||( r4 /2 )} . r 4 acts as the ac load to the dac . the differential ac swing at dac output is 2 i fs r1 ||{ r2 + r3 ||( r4 /2 )}, and the differential ac swing at the m odulator i nput is 2 { r3 ||( r4 /2 )}{ r2 +( r3 ||( r4 /2 )} multiplied by the differential ac swing at dac output . 34.0 218 760 750 20 5.00 31.70 0.50 0.63 1.50 0.34 ?5.43 504 502 setup r1 (?) r2 (?) r3(?) r4 (?) ifs (ma) v1 (v) dac r (single) filter input impedance (?) output impedance (?) dac dac common voltage (v) dac swing (v p_p) (single) mod modulator common voltage (v) mod input swing (v p_p) (single) loss by r2 (db) 09740-014 figure 14. spread s heet for the l evel s hifting c ircuit the lc filter should be placed close to the dac to allow short return cu rrent path . the 5 v bias supply (v1) should be close to the m odulator because it is shared with the m odulator . for the case when r1, r2, r3, and r4 are 34 ?, 218 ?, 760 ? , and 750 ?, respectively, the 500 mv dc bias at the ad9122 dac output is matched to the 1500 mv dc bias at ADL5375 - 15. actually, it is not necessary to be 500 mv at point a of figure 13, but it will give flexibility in the ac swing level without exceeding the compliance voltage of the dac output . the dac load is 31.7 . t he input and output impedance of the filter are 504 and 502 . the attenua tion by r2 , which is the voltage drop by r2 between the dac output and m odulator i nput, is set by the combination of r2 and r3||(r4/2),which is about 5.4 db. to calculate dc bias level and ac swing level at the a and b point s ( figure 1 3) , attenuation by r2 , and source/load impedances of the filter, the spreadsheet below can be used. this can be downloaded at the following url: www.analog.com/cn0205- levelshifter . t he adisimrf tool can also be used to perform dac - m odulator power level calculations. the tool can be download ed from www.analog.com/adisimrf . layout recommendations special care should be taken in the l ayout of the dac /m odulator interface. here are some recommendations. figure 15 shows a top - level layout , which follow s these recommendations : x keep all i/q differential trace lengths well matched . x place filter termination resistor as close as possible to modulator input . x place dac output 50 ? resistors as close as possible to dac . x thicken trace widths through the filter network to reduce signal loss . x place v ias around all dac output traces, filter networks, modulator output trace s, and lo input traces . x route lo and m odulator outputs on different layers o r at 90 angle to each other to prevent coupling . 09740-015 figure 15. general layout recommendation s
circuit note cn-0205 rev. 0 | page 7 of 9 i out1 i out1 20ma to 0ma ad9122 0ma to 20ma 50? spectrum analyzer dpg data pattern generator signal generator for f dac f dac f data ADL5375-05 i out2 i out2 signal generator for lo lo 100? 100? bb filter ad9122-m5375-ebz power supply 5v j9 j1 j6 pc dpg downloader software ad9122 software usb usb 50? 50? 50? bb filter 20ma to 0ma 0ma to 20ma 09740-016 figure 16. test setup functional block diagram further insight to proper layout can be found by examin ing the ad9122 - m5375 - ebz layout files in the design support package www.analog.com/cn0205- designsupport . common variation s the interface described in this circuit note can be used between any txda c digital - to - analog converter ( ad9779a , ad9788 , ad9125 , ad9148 ) that is set for 20 ma full- scale current and t he adl5370 , adl5371 / adl5372 , a dl5373 , adl5374 , adl5385 , adl5386 , etc., family of i/q modulators that require 0.5 v b aseband dc b ias level s. the interface can also be adapted to the ad8345 / ad8349 low current modulators , with some adjustment to the bias level by properly selecting the dac termination resisto rs. circuit evaluation and test the following section describes details of performing the common - mode test (results shown in figure 10). the test setup is flexible and allows other measurements shown in this circuit note to be performed. equipment needed (equivalents c an be substituted) x dpg : adi digital pattern generator x signal g enerator for c lock: agilent e4437b x s ignal generator for lo: agilent 8665b x s pectrum analyzer : agilent e4440a x power supply: agilent e3631a setup and test 1. connect the setup and measurement system shown in figure 16. 2. set the power supply to +5 v. 3. set the signal generator for f dac to 368.64 mhz @ 5 dbm, and the signal generator for lo to 2140 mhz @ 0 dbm. 4. turn on the power supply and signal generators. set the s pectrum analyzer at 2 f dac mhz, 1 mhz span . 5. set up the ad9122 through usb at ad9122 / ad9125 spi control software as shown in figure 1 7 and run. refer to the ad9122 evaluation board quick start guide in www.analog.com- cn0205 - designsupport . x interpolation ( "1" in fig ure 17 ) : 1 x fine m odulation ( "2" in fig ure 17 ) : on x data r at e ( "3" in fig ure 17 ) : same as f dac frequency x nco f requency ( "4" in fig ure 17 ) : 173.32 mhz 6. set up dpg (r efer to ad9122 evaluation board quick start guide) x make sure dco frequency ( "1 " in fig ure 18) is close to fdac frequency . x set sample r ate ( "2" in fig ure 18 ) same as f dac frequency and 1 mhz at desired frequency .
cn-0205 circuit note rev. 0 | page 8 of 9 ? set "3" and " 4 " as shown in figure 1 8. ? download i and q vector by clicking buttons at "1" in fig ure 18 . 7. measure common - mode noise levels at 2 f dac 8. change frequency of signal generator for f d ac , c hange data rate mentioned in (5), and sample rate mentioned in ( 6) 9. measure common - mode noise levels at 2 f dac (new) 10. repeat (8), (9) 09740-017 figure 17. spi control user interface setup for data clock and nco control 09740-018 figure 18. setting up the dpg using the dpg downloader software
circuit note cn-0205 rev. 0 | page 9 of 9 l earn more cn0205 design support package: www.analog.com/cn0205- designsupport mt - 016 tutorial, basic dac architect ures iii: segmented dacs . analog devices. mt - 017 tutorial, oversampling interpolating dacs , analog devices. mt - 031 tutorial, grounding data converters and solving the mystery of 'agnd' and 'dgnd' . analog devices. mt - 101 tutorial, decoupling techniques , analog devices. cn - 0021 circuit note, interfacing the ADL5375 i/q modula tor to the ad9779a dual - channel, 1 gsps high speed dac , analog devices. cn - 0134 circuit note , broadband low evm direct conversion transmitter , analog devices. cn -0 144 circuit note , broadband low evm direct conversion transmitter using lo divide - by - 2 modulator , analog devices. nash, eamon. an - 1039 application note, correcting imperfections in iq modulators to improve rf signal fidelity , analog devices. zhang , yi. an -1 100 application note, wireless tranmitter i /q balance and sideband suppression , analog devices. brandon, david a nd david crook, ken gentile, an - 0996, the advantages of using a quadrature digital upconverter (qduc) in point - to - point microwave transmit systems , analog devices. adisimpll design tool adisimrf design tool ad9122 evaluation board quick start guide analog devices data pattern generator (dpg) data sheets and evaluation boards ad9122 data s heet ADL5375 data s heet ad 9122 evaluation board adl53 75- 05 evaluation board ad 9122- m 5375 - ebz evaluation board revision histo ry 8/11 revision 0 : initial version (continued from first page) circuits from the lab circuits are intended only for use with analog devices products and are the intellectual property of analog devices or its licensors. while you may use the circuits from the lab circuits in the design of your product, no other license is granted by implication or otherwise under any patent s or other intellectual property by application or use of the circuits from the lab circuits. information furnished by analog devic es is believed to be accurate and reliable. however, "circuits from the lab" are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. analog devices reserves the right to change any circuit s from the lab circuits at any time without notice but is under no obligation to do so. ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respec tive owners. cn097 40 -0- 8 /11(0)
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